Master–Slave Flip- Flops Using Transmission Gate By Accessing High Speed Design Values

The basic building blocks of data-path structures are Flipflops. Indeed, data processed by combinational circuits are stored and the operations at a given clock frequency[1] are synchronized in FFs. Speed and energy of FFs affect the overall performance of a data path [2], [3] significantly because of multistage structure, high clock switching activity and increasing portion of clock period occupied by timing latency. Automated algorithms embedded directly into simulators [1],[3],[4] are used as basis in optimal FF design strategies. Even for complicated FFs consisting of several internal nodes, constraints such as speed, energy consumption, or energy-delay products are optimised by these powerful algorithm. For instance, through a proper clock slope setting [5], the joint optimization of FFs and clock networks can be performed by this algorithm.